CY62168G18-55BVXIT

CY62168G is high-performance CMOS low-power (MoBL) SRAM devices with embedded ECC. Both devices are offered in single and dual chip enable options and in multiple pin configurations. Devices with a single chip enable input are accessed by asserting the chip enable input (CE\) LOW. Dual chip enable devices are accessed by asserting both chip enable inputs - CE1\ as LOW and CE2 as HIGH. Write to the device by taking Chip Enable 1 (CE1\) LOW and Chip Enable 2 (CE2) HIGH and the Write Enable (WE\) input LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A20). Read from the device by taking Chip Enable 1 (CE1\) and Output Enable (OE\) LOW and Chip Enable 2 (CE2) HIGH while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE1\ HIGH or CE2 LOW), the outputs are disabled (OE\ HIGH), or a write operation is in progress (CE1\ LOW and CE2 HIGH and WE\ LOW).The CY62168G and CY62168GE devices are available in a Pb-free 48-pin VFBGA package.

• Ultra-low standby power
  • Typical standby current: 5.5 µA
  • Maximum standby current: 16 µA
• High speed: 45 ns / 55 ns
• Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V
• 1.0 V data retention
• Transistor-transistor logic (TTL) compatible inputs and outputs
• ERR pin to indicate 1-bit error detection and correction
• Available in Pb-free 48-ball VFBGA package