CY62162G30-45BGXIT

The CY62162G30 devices is high performance CMOS MoBL SRAM organized as 512K words by 32-bits. Both CY62162G30 is available with dual chip enables. The device also has an automatic power down feature that reduces power consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when deselected (CE1\ HIGH or CE2 LOW or BA\-D HIGH). The input and output pins (I/O0 through I/O31) are placed in a high impedance state when deselected (CE1 HIGH or CE2 LOW) or outputs are disabled (OE HIGH) or the byte selects are disabled (BA-D HIGH). To write to the device, take chip enables (CE1\ LOW, CE2 HIGH) and write enable (WE\) input LOW. If byte enable A (BA\) is LOW, then data from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins (A0 through A18). If byte enable B (BB\) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A18). Likewise, BC\ and BD\ correspond with the I/O pins I/O16 to I/O23 and I/O24 to I/O31, respectively. To read from the device, take chip enables (CE1\ LOW, CE2 HIGH), and output enable (OE\) LOW while forcing the write enable (WE\) HIGH. If the first byte enable (BA\) is LOW, then data from the memory location specified by the address pins appear on I/O0 to I/O7. If byte enable (BB\) is LOW, then data from memory appears on I/O8 to I/O15. Likewise, BC\ and BD\ correspond to the third and fourth bytes. During Read operation, in case of a single bit error detection and correction, ERR is asserted HIGH.

• Ultra-low standby power
  • Typical standby current: 5.5 µA
  • Maximum standby current: 16 µA
• High speed: 45 ns / 55 ns
• Wide voltage: 3.3 V (typ.)
• 1.0-V data retention
• Transistor-transistor logic (TTL) compatible inputs and outputs
• ERR pin to indicate 1-bit error detection and correction
• Easy memory expansion with CE1 and CE2 features
• Available in Pb-free 119-ball PBGA package, 512 K × 32 bits SRAM