CY62147G30-45BVXI

CY62147G is high-performance CMOS low-power (MoBL) SRAM devices with embedded ECC. Both devices are offered in single and dual chip enable options and in multiple pin configurations. Devices with a single chip enable input are accessed by asserting the chip enable (CE\) input LOW. Dual chip enable devices are accessed by asserting both chip enable inputs - CE1\ as low and CE2 as HIGH. Data writes are performed by asserting the Write Enable (WE\) input LOW, while providing the data on I/O0 through I/O15 and address on A0 through A17 pins. The Byte High Enable (BHE\) and Byte Low Enable (BLE\) inputs control write operations to the upper and lower bytes of the specified memory location. BHE\ controls I/O8 through I/O15 and BLE\ controls I/O0 through I/O7. Data reads are performed by asserting the Output Enable (OE\) input and providing the required address on the address lines. Read data is accessible on the I/O lines (I/O0 through I/O15). Byte accesses can be performed by asserting the required byte enable signal (BHE\ or BLE\) to read either the upper byte or the lower byte of data from the specified address location. All I/Os (I/O0 through I/O15) are placed in a HI-Z state when the device is deselected (CE\ HIGH for a single chip enable device and CE1\ HIGH/CE2 LOW for a dual chip enable device), or control signals are deasserted (OE\, BLE\, BHE\). The device also has a unique Byte Power down feature, where, if both the Byte Enables (BHE\ and BLE\) are disabled, the devices seamlessly switch to standby mode irrespective of the state of the chip enables, thereby saving power.

• High speed: 45 ns/55 ns
• Ultra-low standby power
  • Typical standby current: 3.5 µA
  • Maximum standby current: 8.7 µA
• Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V
• 1.0-V data retention
• TTL-compatible inputs and outputs
• Error indication (ERR) pin to indicate 1-bit error detection and correction
• Pb-free 48-ball VFBGA and 44-pin TSOP II packages