CY23S05SXC-1HT

The CY23S09 is a low cost 3.3 V zero delay buffer designed to distribute high speed clocks and is available in a 16-pin SOIC package. The CY23S05 is an 8-pin version of the CY23S09. It accepts one reference input, and drives out five low skew clocks. The -1H versions of each device operate at up to 100 and 133 MHz frequencies and have higher drive than the -1 devices. All parts have on-chip PLLs that lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The CY23S09 has two bans of four outputs each, which can be controlled by the select inputs. If all output clocks are not required, Bank B can be three-stated. The select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes. The CY23S09 and CY23S05 PLLs enter a power down mode when there are no rising edges on the REF input. In this state, the outputs are three-stated and the PLL is turned off, resulting in less than 12.0µA of current draw (for commercial temperature devices) and 25.0 µA (for industrial temperature devices). The CY23S09 PLL shuts down in one additional case. Multiple CY23S09 and CY23S05 devices can accept the same input clock and distribute it. In this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps. All outputs have less than 200 ps of cycle-to-cycle jitter. The input to output propagation delay on both devices is guaranteed to be less than 350 ps; the output to output skew is guaranteed to be less than 250 ps.

• 10 MHz to 100 MHz and 133 MHz operating range, compatible with CPU and PCI bus frequencies
• Zero input-output propagation delay
• Multiple low skew outputs
  • Output-output skew less than 250 ps
  • Device-device skew less than 700 ps
  • One input drives five outputs (CY23S05)
• Less than 200 ps Cycle-to-cycle jitter is compatible with Pentium based systems
• Available in space saving SOIC package (CY23S05)
• 3.3 V operation, advanced 0.65µ CMOS technology
• Spread Aware