CY23EP05SXC-1H

The CY23EP05 is a 2.5 V or 3.3 V zero delay buffer designed to distribute low-jitter high-speed clocks and is available in a 8-pin SOIC package. It accepts one reference input, and drives out five low-skew clocks. The –1H version operates up to 220 (200) MHz frequencies at 3.3 V (2.5 V), and has a higher drive strength than the –1 devices. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The CY23EP05 PLL enters a power-down mode when there are no rising edges on the REF input (< ~2 MHz). In this state, the outputs are three-stated and the PLL is turned off, resulting in less than 25 µA of current draw. The CY23EP05 is available in different configurations, as shown in the Ordering Information table. The CY23EP05-1 is the base part. The CY23EP05-1H is the high-drive version of the –1, and its rise and fall times are much faster than the –1. These parts are not intended for 5 V input-tolerant applications.

• 10 MHz to 220 MHz maximum operating range
• Zero input-output propagation delay, adjustable by loading on CLKOUT pin
• Multiple low-skew outputs
  • 30 ps typical output-output skew
  • One input drives five outputs
• 22 ps typical cycle-to-cycle jitter
• 13 ps typical period jitter
• Standard and high drive strength options
• Available in space-saving 150-mil SOIC package
• 3.3 V or 2.5 V operation
• Industrial temperature available