CY2309SXC-1

CY2309SXC-1 is a CY2309 low-cost 3.3V zero delay buffer designed to distribute high speed clocks. It accepts one reference input, and drives out five low skew clocks. It has on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. This has two banks of four outputs each, which can be controlled by the select inputs. The select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes. The PLLs enter a power-down mode when there are no rising edges on the REF input. In this state, the outputs are three-stated and the PLL is turned off, resulting in less than 25.0µA current draw for these parts.

• Compatible with CPU and PCI bus frequencies, zero input-output propagation delay
• 60ps typical cycle-to-cycle jitter (high drive), multiple low skew outputs
• 85ps typical output-to-output skew, one input drives nine outputs, grouped as 4 + 4 + 1
• Compatible with Pentium-based systems, test mode to bypass phase-locked loop (PLL)
• 16-pin SOIC (150 Mils) package
• 9-output zero delay buffer, commercial temperature range
• Operating temperature (ambient temperature) range from 0 to 70°C