GS880E36CGT-200IV
SRAM Chip Sync Dual 1.8V/2.5V 9M-Bit 256K x 36 6.5ns/3ns 100-Pin TQFP Tray
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Manufacturer:Gsi Technology
Avnet Manufacturer Part #: GS880E36CGT-200IV
Secondary Manufacturer Part#: GS880E36CGT-200IV
-
RoHS 10 Compliant -
Tariff Charges
- FT pin for user-configurable flow through or pipeline operation
- Dual Cycle Deselect (DCD) operation
- 2.5 V or 3.3 V +10%/–10% core power supply
- 2.5 V or 3.3 V I/O supply
- LBO pin for Linear or Interleaved Burst mode
- Internal input resistors on mode pins allow floating mode pins
- Default to Interleaved Pipeline mode
- Byte Write (BW) and/or Global Write (GW) operation
- Internal self-timed write cycle
- Automatic power-down for portable applications
- JEDEC-standard 100-lead TQFP package
- RoHS-compliant 100-lead TQFP package available
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| 18 Bit | ||
| Flow-Through|Pipelined | ||
| 200 MHz | ||
| SDR | ||
| 9 Mbit | ||
| Matte Tin | ||
| 260 | ||
| 145@Flow-Through|170@Pipelined mA | ||
| 2, 2.7 V | ||
| 6.5@Flow-Through|3@Pipelined ns | ||
| 9 Mbit | ||
| 1.7, 2.3 V | ||
| Surface Mount | ||
| MSL 3 - 168 hours | ||
| 100 | ||
| 36 Bit | ||
| 36 Bit | ||
| 2 | ||
| 256 kWords | ||
| -40 to 85 °C | ||
| 85 °C | ||
| -40 °C | ||
| 100TQFP | ||
| 100 | ||
| 20 x 14 x 1.4 mm | ||
| No | ||
| Industrial | ||
| Synchronous SRAM | ||
| TQFP | ||
| 2, 2.7 V | ||
| 1.7, 2.3 V | ||
| 1.8, 2.5 V | ||
| Synchronous | ||
| 1.8, 2.5 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | 3A991.B.2.B |
| HTSN: | 8542320041 |
| Schedule B: | 8542320040 |
Factory Lead Time: