GS8673ET18BGK-550

The family of SRAMs are the Common I/O half of the / family of high performance SRAMs. Although very similar to GSI's second generation of networking SRAMs, the Sigma Quad-II/ -II family, this third generation family of SRAMs offers new features that allow much higher speeds, such as user-configurable on-die input termination, improved output signal integrity, and adjustable pipeline length.

• On-Chip ECC with virtually zero SER
• Configurable Read Latency (3.0 or 2.0 cycles)
• Simultaneous Read and Write Sigma DDR-IIIe™ Interface
• Common I/O Bus
• Double Data Rate interface
• Burst of 2 Read and Write
• Pipelined read operation
• Fully coherent Read and Write pipelines
• 1.35 V nominal VDD
• 1.2 V JESD8-16A BIC-3 Compliant Interface
• 1.5 V HSTL Interface
• ZQ pin for programmable output drive impedance
• ZT for programmable input termination impedance
• Configurable Input Termination
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 260-ball, 14 mm x 22 mm, 1 mm ball pitch BGA package
  • K: 5/6 RoHS-compliant package
  • GK: 6/6 RoHS-compliant package