GS8673EQ18BGK-550

Sigma Quad-IIIe ECCRAMs are the Separate I/O half of the /Sigma DDR-IIIe family of high performance ECCRAMs. Although very similar to GSI's second generation of networking SRAMs (the Sigma Quad-II/Sigma DDR-II family), these third generation devices offer several new features that help enable significantly higher performance.

• For use with GSI SRAM Port IP
• 2Mb x 36 and 4Mb x 18 organizations available
• 725 MHz maximum operating frequency
• 1.45 BT/s peak transaction rate (in billions per second)
• 104 Gb/s peak data bandwidth (in x36 devices)
• Separate I/O DDR Data Buses
• Non-multiplexed DDR Address Bus
• Two operations - Read and Write - per clock cycle
• Burst of 2 Read and Write operations
• 3 cycle Read Latency
• On-chip ECC with virtually zero SER
• 1.35V core voltage
• 1.2V or 1.35V or 1.5V I/O interface (HSTL or SSTL)
• Configurable ODT (on-die termination)
• ZQ pin for programmable driver impedance
• ZT pin for programmable ODT impedance
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 14 mm x 22 mm, 119 BGA
  • K: 5/6 RoHS-compliant package
  • GK: 6/6 RoHS-compliant package
• 64MB or 72MB product family
• Default to SCD x18 Interleaved Pipeline mode