GS8662T38BD-450M
SRAM Chip Sync Single 1.8V 72M-Bit 2M x 36 0.45ns 165-Pin FBGA Bulk
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Manufacturer:Gsi Technology
Avnet Manufacturer Part #: GS8662T38BD-450M
Secondary Manufacturer Part#: GS8662T38BD-450M
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RoHS 10 Compliant -
Tariff Charges
The GS8662T38BD are built in compliance with the -II+ SRAM pin out standard for Common I/O synchronous SRAMs. They are 75,497,472-bit (72Mb) SRAMs. The GS8662T38BD -II+ SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.
- 2.5 Clock Latency
- Simultaneous Read and Write Sigma DDRTM Interface
- JEDEC-standard pin out and package
- Double Data Rate interface
- Byte Write controls sampled at data-in time
- Burst of 2 Read and Write
- On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) inputs
- 1.8 V +100/–100 mV core power supply
- 1.5 V or 1.8 V HSTL Interface
- Pipelined read operation
- Fully coherent read and write pipelines
- ZQ pin for programmable output drive strength
- Data Valid Pin (QVLD) Support
- IEEE 1149.1 JTAG-compliant Boundary Scan
- 13 mm x 15 mm, 165 FPBGA
- RoHS-compliant 165-bump BGA package available
- 6MB product family
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| 20 Bit | ||
| Pipelined | ||
| 450 MHz | ||
| DDR | ||
| 72 Mbit | ||
| 450 MHz | ||
| 0.45 ns | ||
| 72 Mbit | ||
| Surface Mount | ||
| 165 | ||
| 36 Bit | ||
| 36 Bit | ||
| 1 | ||
| 2 MWords | ||
| -55 to 125 °C | ||
| 125 °C | ||
| -55 °C | ||
| 165FBGA | ||
| 165 | ||
| 13 x 15 x 0.94(Max) | ||
| No | ||
| Military | ||
| SigmaDDR SRAM | ||
| FBGA | ||
| 1.8 V | ||
| Synchronous | ||
| 1.8000 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | 3A991.B.2.B |
| HTSN: | 8542320041 |
| Schedule B: | 8542320040 |
Factory Lead Time: