GS8662T36BGD-333
SRAM Chip Sync Single 1.8V 72M-Bit 2M x 36 0.45ns 165-Pin FBGA Tray
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Manufacturer:Gsi Technology
Avnet Manufacturer Part #: GS8662T36BGD-333
Secondary Manufacturer Part#: GS8662T36BGD-333
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RoHS 10 Compliant -
Tariff Charges
The GS8662T36BD is a built in compliance with the SigmaDDR-II SRAM pinout standard for Common I/O synchronous SRAMs. They are 75,497,472-bit (72Mb) SRAMs. The GS8662T36BD SigmaDDR-II SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.
- Simultaneous Read and Write SigmaDDR™ Interface
- Common I/O bus
- JEDEC-standard pinout and package
- Double Data Rate interface
- Byte Write (x36, x18 and x9) and Nybble Write (x8) function
- Burst of 2 Read and Write
- 1.8 V +100/–100 mV core power supply
- 1.5 V or 1.8 V HSTL Interface
- Pipelined read operation with self-timed Late Write
- Fully coherent read and write pipelines
- ZQ pin for programmable output drive strength
- IEEE 1149.1 JTAG-compliant Boundary Scan
- Pin-compatible with present 9Mb, 18Mb, 36Mb and 72Mb devices
- 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
- RoHS-compliant 165-bump BGA package available
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| 21 Bit | ||
| Pipelined | ||
| 333 MHz | ||
| DDR | ||
| 72 Mbit | ||
| Tin-Silver-Copper | ||
| 260 | ||
| 333 MHz | ||
| 685 mA | ||
| 0.45 ns | ||
| 72 Mbit | ||
| Surface Mount | ||
| MSL 3 - 168 hours | ||
| 165 | ||
| 36 Bit | ||
| 36 Bit | ||
| 1 | ||
| 2 MWords | ||
| 0 to 85 °C | ||
| 85 °C | ||
| 0 °C | ||
| 165FBGA | ||
| 165 | ||
| 15 x 13 x 0.94 mm | ||
| No | ||
| Commercial | ||
| SigmaDDR SRAM | ||
| FBGA | ||
| 1.8 V | ||
| Synchronous | ||
| 1.8000 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | 3A991.B.2.B |
| HTSN: | 8542320041 |
| Schedule B: | 8542320040 |
Factory Lead Time: