GS8662S18BD-333
SRAM Chip Sync Dual 1.8V 72M-Bit 4M x 18 0.45ns 165-Pin FBGA Tray
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Manufacturer:Gsi Technology
Avnet Manufacturer Part #: GS8662S18BD-333
Secondary Manufacturer Part#: GS8662S18BD-333
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RoHS 10 Compliant -
Tariff Charges
GS8662S18BD are built in compliance with the Sigma SIO DDR-II SRAM pin out standard for Separate I/O synchronous SRAMs. They are 75,497,472-bit (72Mb) SRAMs. These are the first in a family of wide, very low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.
- Simultaneous Read and Write Sigma SIO™ Interface
- JEDEC-standard pin out and package
- Dual Double Data Rate interface
- Byte Write controls sampled at data-in time
- DLL circuitry for wide output data valid window and future frequency scaling
- Burst of 2 Read and Write
- 1.8 V +100/–100 mV core power supply
- 1.5 V or 1.8 V HSTL Interface
- Pipelined read operation
- Fully coherent read and write pipelines
- ZQ mode pin for programmable output drive strength
- IEEE 1149.1 JTAG-compliant Boundary Scan
- 13 mm x 15 mm, 165 FPBGA
- RoHS-compliant 165-bump BGA package available
- 6MB product family
- Default to SCD x18 Interleaved Pipeline mode
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| 21 Bit | ||
| Pipelined | ||
| 333 MHz | ||
| DDR | ||
| 72 Mbit | ||
| Tin-Lead | ||
| 333 MHz | ||
| 630 mA | ||
| 0.45 ns | ||
| 72 Mbit | ||
| Surface Mount | ||
| 165 | ||
| 18 Bit | ||
| 18 Bit | ||
| 2 | ||
| 4 MWords | ||
| 0 to 85 °C | ||
| 85 °C | ||
| 0 °C | ||
| 165FBGA | ||
| 165 | ||
| 15 x 13 x 0.94 mm | ||
| No | ||
| Commercial | ||
| SigmaSIO DDR SRAM | ||
| FBGA | ||
| 1.8 V | ||
| Synchronous | ||
| 1.8000 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | 3A991.B.2.B |
| HTSN: | 8542320041 |
| Schedule B: | 8542320040 |
Factory Lead Time: