GS8640FZ18GT-6.5

The GS8640FZ18/36T-xxxV is a 72Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NoBL or other flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.The GS8640FZ18/36T-xxxV is implemented with GSI's high performance CMOS technology and is available in a JEDEC-standard 100-pin TQFP package.

• NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization; Fully pin-compatible with flow through ™, NoBL™ and ZBT™ SRAMs
• 1.8 V or 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Pin compatible with 4Mb, 9Mb, 18Mb and 36Mb devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP package
• RoHS-compliant 100-lead TQFP package available