GS8342TT38BGD-500
SRAM Chip Sync Single 1.8V 36M-Bit 1M x 36 0.45ns 165-Pin FBGA
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Manufacturer:Gsi Technology
Avnet Manufacturer Part #: GS8342TT38BGD-500
Secondary Manufacturer Part#: GS8342TT38BGD-500
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RoHS 10 Compliant -
Tariff Charges
The GS8342TT38BD are built in compliance with the SigmaDDR-II+ SRAM pinout standard for Common I/O synchronous SRAMs. They are 37,748,736-bit (36Mb) SRAMs. The GS8342TT06/11/20/38BD SigmaDDR-II+ SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.
- 2.5 Clock Latency
- Simultaneous Read and Write SigmaDDRTM Interface
- JEDEC-standard pinout and package
- Double Data Rate interface
- Byte Write controls sampled at data-in time
- Burst of 2 Read and Write
- Dual-Range On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) inputs
- 1.8 V +100/–100 mV core power supply
- 1.5 V or 1.8 V HSTL Interface
- Pipelined read operation
- Fully coherent read and write pipelines
- ZQ pin for programmable output drive strength
- Data Valid Pin (QVLD) Support
- IEEE 1149.1 JTAG-compliant Boundary Scan
- 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
- RoHS-compliant 165-bump BGA package available
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| 19 Bit | ||
| Pipelined | ||
| 500 MHz | ||
| DDR | ||
| 36 Mbit | ||
| 500 MHz | ||
| 945 mA | ||
| 0.45 ns | ||
| 36 Mbit | ||
| Surface Mount | ||
| 165 | ||
| 36 Bit | ||
| 36 Bit | ||
| 1 | ||
| 1 MWords | ||
| 0 to 85 °C | ||
| 85 °C | ||
| 0 °C | ||
| 165FBGA | ||
| 165 | ||
| 15 x 13 x 0.94 mm | ||
| No | ||
| Commercial | ||
| SigmaDDR SRAM | ||
| FBGA | ||
| 1.8 V | ||
| Synchronous | ||
| 1.8000 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | 3A991.B.2.B |
| HTSN: | 8542320041 |
| Schedule B: | 8542320040 |
Factory Lead Time: