GS8342T37BGD-300

The GS8342T37BD is a built in compliance with theSigmaDDR-II+ SRAM pinout standard for Common I/Osynchronous SRAMs. They are 37,748,736 (36Mb) SRAMs. The GS8342T37BD SigmaDDR-II+ SRAMs are justone element in a family of low power, low voltage HSTL I/OSRAMs designed to operate at the speeds needed to implementeconomical high performance networking systems.

• 2.0 Clock Latency
• Simultaneous Read and Write SigmaDDR™ Interface
• Common I/O bus
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 2 Read and Write
• On-Die Termination (ODT) on Data (D), Byte Write, and Clock (K) inputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available