GS8342S18BGD-400
SRAM Chip Sync Dual 1.8V 36M-Bit 2M x 18 0.45ns 165-Pin FBGA
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Manufacturer:Gsi Technology
Avnet Manufacturer Part #: GS8342S18BGD-400
Secondary Manufacturer Part#: GS8342S18BGD-400
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RoHS 10 Compliant -
Tariff Charges
GS8342S18BD is a built in compliance with the SigmaSIO DDR-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 37,748,736-bit (36Mb) SRAMs. These are the first in a family of wide, very low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.
- Simultaneous Read and Write SigmaSIO™ Interface
- JEDEC-standard pinout and package
- Dual Double Data Rate interface
- Byte Write controls sampled at data-in time
- DLL circuitry for wide output data valid window and future frequency scaling
- Burst of 2 Read and Write
- 1.8 V +100/–100 mV core power supply
- 1.5 V or 1.8 V HSTL Interface
- Pipelined read operation
- Fully coherent read and write pipelines
- ZQ mode pin for programmable output drive strength
- IEEE 1149.1 JTAG-compliant Boundary Scan
- 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
- RoHS-compliant 165-bump BGA package available
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| 20 Bit | ||
| Pipelined | ||
| 400 MHz | ||
| DDR | ||
| 36 Mbit | ||
| 400 MHz | ||
| 705 mA | ||
| 0.45 ns | ||
| 36 Mbit | ||
| Surface Mount | ||
| 165 | ||
| 18 Bit | ||
| 18 Bit | ||
| 2 | ||
| 2 MWords | ||
| 0 to 85 °C | ||
| 85 °C | ||
| 0 °C | ||
| 165FBGA | ||
| 165 | ||
| 15 x 13 x 0.94 mm | ||
| No | ||
| Commercial | ||
| SigmaSIO DDR SRAM | ||
| FBGA | ||
| 1.8 V | ||
| Synchronous | ||
| 1.8000 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | 3A991.B.2.B |
| HTSN: | 8542320041 |
| Schedule B: | 8542320040 |
Factory Lead Time: