GS8342Q36BD-357I

The GS8342Q36BD are built in compliance with the Sigma Quad-II SRAM pin out standard for Separate I/O synchronous SRAMs. They are 37,748,736-bit (36Mb) SRAMs. The GS8342Q36BD Sigma Quad SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.

• Simultaneous Read and Write Sigma Quad™ Interface
• JEDEC-standard pin out and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with present 144 Mb devices
• 13 mm x 15 mm, 165 FPBGA
• RoHS-compliant 165-bump BGA package available
• 32MB or 36MB product family
• Default to SCD x36 Interleaved Pipeline mode