GS8342DT06BD-550I

The GS8342DT06BD are built in compliance with the Sigma Quad-II+ SRAM pin out standard for Separate I/O synchronous SRAMs. They are 37,748,736-bit (36Mb) SRAMs. The GS8342DT06BD Sigma Quad SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.

• 2.5 Clock Latency
• Simultaneous Read and Write Sigma Quad™ Interface
• JEDEC-standard pin out and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 4 Read and Write
• Dual-Range On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K)inputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid Pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 13 mm x 15 mm, 165 FPBGA
• RoHS-compliant 165-bump BGA package available
• 32MB or 36MB product family