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GS8342D36BD-250I

SRAM Chip Sync Dual 1.8V 36M-Bit 1M x 36 0.45ns 165-Pin FBGA

Manufacturer:Gsi Technology
Product Category: Memory, SRAMs
Avnet Manufacturer Part #: GS8342D36BD-250I
Secondary Manufacturer Part#: GS8342D36BD-250I
  • Legend Information Icon RoHS 10 Compliant
  • Legend Information Icon Tariff Charges

The GS8342D36BD is a built in compliance with the Sigma Quad-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 37,748,736-bit (36Mb) SRAMs. The GS8342D36BD Sigma Quad SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.Clocking and Addressing Schemes: The GS8342D36BD Sigma Quad-II SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. The device also allows the user to manipulate the output register clock inputs quasi independently with the C and C clock inputs. C and C are also independent single-ended clock inputs, not differential inputs. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead.Each internal read and write operation in a Sigma Quad-II B4 RAM is four times wider than the device I/O bus. An input data bus de-multiplexer is used to accumulate incoming data before it is simultaneously written to the memory array. An output data multiplexer is used to capture the data produced from a single memory array read and then route it to the appropriate output drivers as needed. Therefore the address field of a Sigma Quad-II B4 RAM is always two address pins less than the advertised index depth (e.g., the 4M x 8 has a 1M addressable index).

  • Simultaneous Read and Write Sigma Quad™ Interface
  • JEDEC-standard pinout and package
  • Dual Double Data Rate interface
  • Byte Write controls sampled at data-in time
  • Burst of 4 Read and Write
  • 1.8 V +100/–100 mV core power supply
  • 1.5 V or 1.8 V HSTL Interface
  • Pipelined read operation
  • Fully coherent read and write pipelines
  • ZQ pin for programmable output drive strength
  • IEEE 1149.1 JTAG-compliant Boundary Scan
  • Pin-compatible with present 144 Mb devices
  • 3rd Generation, Green, 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
  • RoHS-compliant 165-bump BGA package available

Technical Attributes

Find Similar Parts

Description Value
18 Bit
Pipelined
250 MHz
QDR
36 Mbit
250 MHz
685 mA
0.45 ns
36 Mbit
Surface Mount
165
36 Bit
36 Bit
2
1 MWords
-40 to 100 °C
100 °C
-40 °C
165FBGA
165
15 x 13 x 0.94 mm
No
Industrial
SigmaQuad SRAM
FBGA
1.8 V
Synchronous
1.8000 V

ECCN / UNSPSC / COO

Description Value
Country of Origin: RECOVERY FEE
ECCN: 3A991.B.2.B
HTSN: 8542320041
Schedule B: 8542320040
In Stock :  0
Additional inventory
Factory Lead Time: 168 Weeks
Price for: Each
Quantity:
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144+
$39.2733
288+
$39.07495
576+
$38.8766
864+
$38.67825
1152+
$38.4799