GS8321E18AD-333V
SRAM Chip Sync Dual 1.8V/2.5V 36M-Bit 2M x 18 5ns/3ns 165-Pin FBGA
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Manufacturer:Gsi Technology
Avnet Manufacturer Part #: GS8321E18AD-333V
Secondary Manufacturer Part#: GS8321E18AD-333V
-
RoHS 10 Compliant -
Tariff Charges
- FT pin for user-configurable flow through or pipeline operation
- Dual Cycle Deselect (DCD) operation
- IEEE 1149.1 JTAG-compatible Boundary Scan
- 2.5 V or 3.3 V +10%/–10% core power supply
- 2.5 V or 3.3 V I/O supply
- LBO pin for Linear or Interleaved Burst mode
- Internal input resistors on mode pins allow floating mode pins
- Default to Interleaved Pipeline mode
- Byte Write (BW) and/or Global Write (GW) operation
- Internal self-timed write cycle
- Automatic power-down for portable applications
- JEDEC-standard 165-bump BGA package
- Rosh-compliant 165-bump BGA package available
- 2nd Generation, 13 mm x 15 mm, 165 FPBGA
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| 21 Bit | ||
| Flow-Through|Pipelined | ||
| 333 MHz | ||
| SDR | ||
| 36 Mbit | ||
| 245@Flow-Through|345@Pipelined mA | ||
| 2, 2.7 V | ||
| 5@Flow-Through|3@Pipelined ns | ||
| 36 Mbit | ||
| 1.7, 2.3 V | ||
| Surface Mount | ||
| 165 | ||
| 18 Bit | ||
| 18 Bit | ||
| 2 | ||
| 2 MWords | ||
| 0 to 85 °C | ||
| 85 °C | ||
| 0 °C | ||
| 165FBGA | ||
| 165 | ||
| 15 x 13 x 0.94 mm | ||
| No | ||
| Commercial | ||
| Synchronous SRAM | ||
| FBGA | ||
| 2, 2.7 V | ||
| 1.7, 2.3 V | ||
| 1.8, 2.5 V | ||
| Synchronous | ||
| 1.8, 2.5 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | 3A991.B.2.B |
| HTSN: | 8542320041 |
| Schedule B: | 8542320040 |
Factory Lead Time: