GS82583ED18GK-675

Sigma Quad-IIIe SRAMs are the Separate I/O half of the /Sigma DDR-IIIe family of high performance SRAMs. Although very similar to GSI's second generation of networking SRAMs (the Sigma Quad-II/Sigma DDR-II family), these third generation devices offer several new features that help enable significantly higher performance.

• 8Mb x 36 and 16Mb x 18 organizations available
• 675 MHz maximum operating frequency
• 675 MT/s peak transaction rate (in millions per second)
• 97 Gb/s peak data bandwidth (in x36 devices)
• Separate I/O DDR Data Buses
• Non-multiplexed SDR Address Bus
• One operation - Read or Write - per clock cycle
• Burst of 4 Read and Write operations
• 3 cycle Read Latency
• 1.3V nominal core voltage
• 1.2V, 1.3V, or 1.5V HSTL I/O interface
• Configurable ODT (on-die termination)
• ZQ pin for programmable driver impedance
• ZT pin for programmable ODT impedance
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS compliant BGA package