GS816272CC-200IV
SRAM Chip Sync Octal 1.8V/2.5V 18M-Bit 256K x 72-Bit 6.5ns/3ns 209-Pin BGA Tray
- RoHS 10 Compliant
- Tariff Charges
- FT pin for user-configurable flow through or pipeline operation
- Single/Dual Cycle Deselect selectable
- IEEE 1149.1 JTAG-compatible Boundary Scan
- ZQ mode pin for user-selectable high/low output drive
- 2.5 V or 3.3 V +10%/–10% core power supply
- LBO pin for Linear or Interleaved Burst mode
- Internal input resistors on mode pins allow floating mode pins
- Default to SCD x18/x36 Interleaved Pipeline mode
- Byte Write (BW) and/or Global Write (GW) operation
- Internal self-timed write cycle
- Automatic power-down for portable applications
- JEDEC-standard 209-bump BGA package
- RoHS-compliant 209-bump BGA package available
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| 18 Bit | ||
| Flow-Through|Pipelined | ||
| 200 MHz | ||
| SDR | ||
| 18 Mbit | ||
| Tin-Lead | ||
| 240@Flow-Through|300@Pipelined mA | ||
| 2, 2.7 V | ||
| 6.5@Flow-Through|3@Pipelined ns | ||
| 256K x 72bit | ||
| 18 Mbit | ||
| 1.7, 2.3 V | ||
| Surface Mount | ||
| 209 | ||
| 72 Bit | ||
| 72 Bit | ||
| 8 | ||
| 256 kWords | ||
| -40 to 85 °C | ||
| 85 °C | ||
| -40 °C | ||
| 209BGA | ||
| 209 | ||
| 22 x 14 x 1.1 mm | ||
| No | ||
| Industrial | ||
| Synchronous SRAM | ||
| BGA | ||
| 2, 2.7 V | ||
| 1.7, 2.3 V | ||
| 1.8, 2.5 V | ||
| Synchronous | ||
| 1.8, 2.5 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | 3A991.B.2.B |
| HTSN: | 8542320041 |
| Schedule B: | 8542320040 |