GS816236DGD-250V
SRAM Chip Sync Quad 1.8V/2.5V 18M-Bit 512K x 36 5.5ns/3ns 165-Pin FBGA
- RoHS 10 Compliant
- Tariff Charges
- FT pin for user-configurable flow through or pipeline operation
- Single/Dual Cycle Deselect selectable
- IEEE 1149.1 JTAG-compatible Boundary Scan
- ZQ mode pin for user-selectable high/low output drive
- 1.8 V or 2.5 V core power supply
- 1.8 V or 2.5 V I/O supply
- LBO pin for Linear or Interleaved Burst mode
- Internal input resistors on mode pins allow floating mode pins
- Default to SCD x18/x36 Interleaved Pipeline mode
- Byte Write (BW) and/or Global Write (GW) operation
- Internal self-timed write cycle
- Automatic power-down for portable applications
- JEDEC-standard 119- and 165-bump BGA packages
- RoHS-compliant packages available
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| 19 Bit | ||
| Flow-Through|Pipelined | ||
| 250 MHz | ||
| SDR | ||
| 18 Mbit | ||
| 225@Flow-Through|245@Pipelined mA | ||
| 2, 2.7 V | ||
| 5.5@Flow-Through|3@Pipelined ns | ||
| 512K x 36bit | ||
| 18 Mbit | ||
| 1.7, 2.3 V | ||
| Surface Mount | ||
| 165 | ||
| 36 Bit | ||
| 36 Bit | ||
| 4 | ||
| 512 kWords | ||
| 0 to 85 °C | ||
| 85 °C | ||
| 0 °C | ||
| 165FBGA | ||
| 165 | ||
| 15 x 13 x 0.94 mm | ||
| No | ||
| Commercial | ||
| Synchronous SRAM | ||
| FBGA | ||
| 2, 2.7 V | ||
| 1.7, 2.3 V | ||
| 1.8, 2.5 V | ||
| Synchronous | ||
| 1.8, 2.5 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | 3A991.B.2.B |
| HTSN: | 8542320041 |
| Schedule B: | 8542320040 |