GS81302S18GE-250I
SRAM Chip Sync Dual 1.8V 144M-Bit 8M x 18 0.45ns 165-Pin FBGA Tray
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Manufacturer:Gsi Technology
Avnet Manufacturer Part #: GS81302S18GE-250I
Secondary Manufacturer Part#: GS81302S18GE-250I
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RoHS 10 Compliant -
Tariff Charges
GS81302S18E is built in compliance with the Sigma SIO DDR-II SRAM pin out standard for Separate I/O synchronous SRAMs. They are 150,994,944-bit (144Mb) SRAMs. These are the first in a family of wide, very low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.
- Simultaneous Read and Write Sigma SIO™ Interface
- JEDEC-standard pin out and package
- Dual Double Data Rate interface
- Byte Write controls sampled at data-in time
- DLL circuitry for wide output data valid window and future frequency scaling
- Burst of 2 Read and Write
- 1.8 V +100/–100 mV core power supply
- 1.5 V or 1.8 V HSTL Interface
- Pipelined read operation
- Fully coherent read and write pipelines
- ZQ mode pin for programmable output drive strength
- IEEE 1149.1 JTAG-compliant Boundary Scan
- 15 mm x 17 mm, 165 FPBGA
- RoHS-compliant 165-bump BGA package available
- 1MB product Family
- Default to SCD x18 Interleaved Pipeline mode
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| 22 Bit | ||
| Pipelined | ||
| 250 MHz | ||
| DDR | ||
| 144 Mbit | ||
| Tin-Silver-Copper | ||
| 260 | ||
| 250 MHz | ||
| 710 mA | ||
| 0.45 ns | ||
| 8M x 18bit | ||
| 144 Mbit | ||
| Surface Mount | ||
| MSL 3 - 168 hours | ||
| 165 | ||
| 18 Bit | ||
| 18 Bit | ||
| 2 | ||
| 8 MWords | ||
| -40 to 100 °C | ||
| 100 °C | ||
| -40 °C | ||
| 165FBGA | ||
| 165 | ||
| 17 x 15 x 1.04 mm | ||
| No | ||
| Industrial | ||
| SigmaSIO DDR SRAM | ||
| FBGA | ||
| 1.8 V | ||
| Synchronous | ||
| 1.8000 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | 3A991.B.2.B |
| HTSN: | 8542320041 |
| Schedule B: | 8542320040 |
Factory Lead Time: