GS81302R08E-375I
SRAM Chip Sync Dual 1.8V 144M-Bit 16M x 8 0.45ns 165-Pin FBGA Tray
- RoHS 10 Compliant
- Tariff Charges
The GS81302R08E are built in compliance with the Sigma DDR-II SRAM pin out standard for Common I/O synchronous SRAMs. They are 150,994,944-bit (144Mb) SRAMs. The GS81302R08/09/18/36E -II SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.
- Simultaneous Read and Write ™ Interface
- Common I/O bus
- JEDEC-standard pin out and package
- Double Data Rate interface
- Byte Write (x36 and x18) and Nibble Write (x8) function
- Burst of 4 Read and Write
- 1.8 V +100/–100 mV core power supply
- 1.5 V or 1.8 V HSTL Interface
- Pipelined read operation with self-timed Late Write
- Fully coherent read and write pipelines
- ZQ pin for programmable output drive strength
- IEEE 1149.1 JTAG-compliant Boundary Scan
- Pin-compatible with present 9Mb, 18Mb, 36Mb and 72Mb devices
- 15 mm x 17 mm, 165 FPBGA
- RoHS-compliant 165-bump BGA package available
- 1MB product Family
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| 22 Bit | ||
| Pipelined | ||
| 375 MHz | ||
| DDR | ||
| 144 Mbit | ||
| 375 MHz | ||
| 855 mA | ||
| 0.45 ns | ||
| 16M x 8bit | ||
| 144 Mbit | ||
| Surface Mount | ||
| 165 | ||
| 8 Bit | ||
| 8 Bit | ||
| 2 | ||
| 16 MWords | ||
| -40 to 100 °C | ||
| 100 °C | ||
| -40 °C | ||
| 165FBGA | ||
| 165 | ||
| 17 x 15 x 1.04 mm | ||
| No | ||
| Industrial | ||
| SigmaDDR SRAM | ||
| FBGA | ||
| 1.8 V | ||
| Synchronous | ||
| 1.8000 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | 3A991.B.2.B |
| HTSN: | 8542320041 |
| Schedule B: | 8542320040 |