74LVC1G07W5-7

74LVC1G07W5-7 is a single buffer gate with an open-drain output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The input is tolerant to 5.5V allowing this device to be used in a mixed voltage environment. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow when the device is powered down. The open-drain output can be connected to other open drain outputs to implement active-low wired-OR or active-high wired-AND functions. Typical applications include voltage level shifting, general purpose logic, power down signal isolation, wide array of products such as PCs, networking, notebooks, netbooks, PDAs, tablet computers, E-readers, computer peripherals, hard drives, CD/DVD ROM, TV, DVD, DVR, set top box, cell phones, personal navigation/GPS, MP3 players, cameras, video recorders.

• CMOS low power consumption
• Ioff supports partial-power-down mode operation
• Latch-up exceeds 100mA per JESD 78, class I
• Direct interface with TTL levels
• Operating voltage is 1.65V minimum at TA=+25°C
• Output voltage is 5.5V maximum at TA=+25°C
• Input transition rise or fall rate is 20ns/V typ at VCC=1.8V ±0.15V, 2.5V ±0.2V
• SOT25 package
• Operating free-air temperature range from -40 to 125°C