PEX8748-CA80BC G

The Express Lane PEX 8748 device offers Multi-Host PCI Express switching capability enabling users to connect multiple hosts to their respective endpoints via scalable, high bandwidth, non-blocking interconnection to a wide variety of applications including servers, storage, communications, and graphics platforms. The PEX 8748 is well suited for fan-out. aggregation, and peer-to-peer traffic patterns. The PEX 8748 employs an enhanced version of PLX's field tested PEX 8648 PCIe switch architecture, which allows users to configure the device in legacy single-host mode or multi-host mode with up to six host ports capable of 1 + 1 (one active & one backup) or N+1 (N active & one backup) host failover. This powerful architectural enhancement enables users to build PCIe based systems to support high-availability, failover, redundant, or clustered systems. The PEX 8748 architecture supports packet cut-thru with a maximum latency of 100ns (xl6 to \16). This, combined with large packet memory, flexible common buffer/FC credit pool and non-blocking internal switch architecture, provides full line rate on all ports for performance-hungry applications such as servers and switch fabrics. The low latency enables applications to achieve high throughput and performance. In addition to low latency, the device supports a packet payload size of up to 2048 bytes, enabling the user to achieve even higher throughput. The PEX 8748 provides end-to-end CRC (ECRC) protection and Poison bit support to enable designs that require end-to-end data integrity. PLX also supports data path parity and memory (RAM) error correction circuitry throughout the internal data paths as packets pass through the switch.

• 48-lane, 12-port PCIe Gen 3 switch
• Integrated 8.0 GT/s SerDes
• 27 x 27mm\ 676-pin FCBGA package
• Typical Powder: 8.0 Watts
• Standards Compliant
  • PCI Express Base Specification, r3.0 (compatible w/ PCIe r1.0a/1.1 & 2.0)
  • PCI Power Management Spec, r1.2
  • Microsoft Vista Compliant
  • Supports Access Control Services
  • Dynamic link-width control
  • Dynamic ScrDcs speed control
• High Performance
  • performance PAK
  • Read Pacing (bandwidth throttling)
  • Multicast
  • Dynamic Buffer/FC Credit Pool
  • Non-blocking switch fabric
  • Full line rate on all ports
  • Packet Cut-Thru with 100ns max packet latency (x16 to x16)
  • 2KB Max Payload Size
• Flexible Configuration
  • Ports configurable as x 1, x2, x4, x8, x 16
  • Registers configurable w ith strapping pins, EEPROM, I*C, or host software
  • Lane and polarity reversal
  • Compat