BCM82381BKFSBG

The BCM82381 is a low-power, low latency PHY integrating re-timer and equalizer functions that support 100-Gigabit Ethernet (GbE), 40GbE, and 10GbE applications. In 100G mode, the BCM82381 supports two full-duplex 100G ports (CAUI4-to-CAUI4) for SR4, LR4, and copper CR4 CFP2/CFP4/QSFP2 line-card applications. In 40G mode, the BCM82381 supports two full-duplex 40GbE ports (XLPPI-to-XLAUI) for SR4, LR4, and copper CR4 QSFP+ line-card applications. In 10G mode, the BCM82381 supports eight full-duplex 10GbE ports (SFI-to-XFI) for SR, LR, and copper CR SFP+ line-card applications.

On-chip clock synthesis is performed by a dual low cost 156.25 MHz reference clock (for all IEEE Standard 10G/40G/100G rates) via high-frequency, low jitter phase-locked loops (PLLs). Individual clock recovery is performed on the device by synchronizing directly to the respective incoming data streams.

The BCM82381 was designed in 28 nm CMOS technology to provide a low-power (<2.5W per 100G full-duplex port, including 100G FEC), low-latency (<5 ns round trip) solution with integrated AC coupling capacitors for direct interfacing to switch products.

The BCM82381 is available in a 19 mm x 19 mm, 324-pin BGA, RoHS-compliant package.

• Dual 100GbE ports with CAUI4-to-CAUI4 port support SR4/LR4/CR4 CFP2/CFP4/QSFP2 retimer/equalization applications
• Dual 40GbE channels with two XLPPI-to-XLAUI ports support SR4/LR4/CR4 QSFP+ retimer/ equalization applications
• 10G mode with eight independent 10GbE/ 1GbE SFI-to-XFI channels support SR/LR/CR SFP+ retimer/equalization applications. Supports an intermix of 1GbE and 10GbE operations on a per-lane basis
• Low-latency design (<5 ns round trip). Low-power retimer/equalizer PHY (<2.5W per 100GbE bidirectional port, including 100G FEC; equivalent to <300 mW per 25G unidirectional channel for 25G retiming mode)
• Seamless high-speed I/O routing to modules
• Integrated AC-coupling capacitors on all highspeed receivers
• High-performance receive equalization ~ 30 dB at system side and ~ 35 dB at line side for channel loss
• Programmable transmit preemphasis for flexible PHY placement
• IEEE 802.3bj 100GbE CR4 Clause 92 transm