BCM56450B1KFSBG

Combines a feature-rich packet processing engine, an integrated hierarchical traffic manager, a deep external packet buffer and a non--blocking switch fabric into a single 40 nm CMOS device.

The StrataXGS BCM56450 is ninth generation of the StrataXGS product line. The StrataXGS BCM56450 is purpose-built for next-generation Carrier Ethernet Edge and Mobile Backhaul platforms. The StrataXGS BCM56450 supports an integrated packet buffer with an external packet buffer expansion option, using economical DDR3 SDRAM technology. The StrataXGS BCM56450 is capable of handling L2 switching, L3 routing, Metro VPN tunneling and Access Control Lists (ACLs). The StrataXGS BCM56450's virtualized architecture enables seamless support for VPLS, VPWS, MPLS-TP, PBB and PBB-TE tunneling. The StrataXGS BCM56450 also offers unparalleled integration for supporting Ethernet time synchronization. Synchronous Ethernet Clock recovery is supported on any port to enable physical layer clock synchronization. In addition to physical layer clock synchronization, the StrataXGS BCM56450 supports both IEEE 1588v2 and IEEE 802.1as packet-based clock synchronization.

• Advanced OAM functions and hardware-based protection switching enable a highly reliable backhaul network
• Carrier Ethernet packet processor delivers line-rate L2 and VLAN switching, L3 routing, MPLS, MPLS-TP and provider backbone bridging (PBB) while supporting L2, L3, MPLS or PBB deployment models
• On-chip ARM-based CPU and integrated 10G optical PHYs reduce bill-of-materials cost and enable a compact system design
• Highly integrated, purpose-built solution for fixed and modular systems
• Deep buffer for lossless delivery of services