XCZU9EG-L2FFVB1156E

Xilinx® UltraScale architecture comprises high-performance FPGA and MPSoC families that address a vast spectrum of system requirements with a focus on lowering total power consumption through numerous innovative technological advancements. Kintex® UltraScale FPGAs: High-performance FPGAs with a focus on price/performance, using both monolithic and next-generation stacked silicon interconnect (SSI) technology. High DSP and block RAM-to-logic ratios and next-generation transceivers, combined with low-cost packaging, enable an optimum blend of capability and cost. Kintex UltraScale+ FPGAs: Based on the UltraScale architecture, these devices have increased performance and on-chip UltraRAM memory to reduce BOM cost, providing the ideal mix of high-performance peripherals and cost-effective system implementation. In addition, Kintex UltraScale+ FPGAs have numerous power options that deliver the optimal balance between the required system performance and the smallest power envelope. Virtex® UltraScale FPGAs: The industry's most capable high-performance FPGAs enabled using both monolithic and next-generation SSI technology to achieve the highest system capacity, bandwidth, and performance. Variants of the Virtex UltraScale family are optimized to address key market and application requirements through integration of various system-level functions, delivering unprecedented embedded memory and serial connectivity capabilities. Virtex UltraScale+ FPGAs: Based on the UltraScale architecture, these devices have the highest transceiver bandwidth, highest DSP count, and highest on-chip memory available in the industry for the ultimate in system performance. In addition, Virtex UltraScale+ FPGAs also provide numerous power options that deliver the optimal balance between the required system performance and the smallest power envelope. Zynq® UltraScale+ MPSoCs: Combine the ARM® v8-based Cortex®-A53 high-performance energy-efficient 64-bit application processor with the ARM Cortex-R5

UltraScale+ MPSoCs are built around a feature-rich quad-core ARM Cortex-A53 and dual-core ARM Cortex-R5 processing system (PS). In addition to the 32-bit/64-bit application processing unit (APU) and 32-bit real-time processing unit (RPU), the PS contains a dedicated ARM Mali™-400 MP2 graphics processing unit (GPU). To support the processors' functionality, a number of peripherals with dedicated functions are included in the PS. For interfacing to external memories for data or configuration storage, the PS includes a multi-protocol dynamic memory controller, a DMA controller, a NAND controller, an SD/eMMC controller and a Quad SPI controller. In addition to interfacing to external memories, the processing units also contain their level 1 and/or level 2 caches and 256KB of on-chip memory. For high-speed interfacing, the PS includes 4 channels of transmit (TX) and receive (RX) pairs of transceivers, called PS-GTR transceivers, supporting data rates of up to 6.0Gb/s. These transceivers can