XA6SLX75T-3FGG484Q

The Xilinx Automotive (XA) Spartan®-6 family of FPGAs provides leading system integration capabilities with the lowest total cost for highvolume automotive applications. The ten-member family delivers expanded densities ranging from 3,840 to 101,261 logic cells and faster, more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that delivers the optimal balance of cost, power, and performance, the XA Spartan-6 family offers a new, more efficient, dual-register 6-input look-up table (LUT) logic and a rich selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO technology, power-optimized high-speed serial transceiver blocks, PCI Express® compatible Endpoint blocks, advanced system-level power management modes, auto-detect configuration options, and enhanced IP security with AES and Device DNA protection. These features provide a low-cost programmable alternative to custom ASIC products with unprecedented ease of use. XA Spartan-6 FPGAs offer the best solution for flexible and scalable high-volume logic designs, high-bandwidth parallel DSP processing designs, and cost-sensitive applications where multiple interfacing standards are required. XA Spartan-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components that enable designers to focus on innovation as soon as their development cycle begins.

• XA Spartan-6 LXT FPGA: High-speed serial connectivity
• Automotive Temperatures:
• I-Grade: Tj = –40°C to +100°C
• Q-Grade: Tj = –40°C to +125°C
• Automotive Standards:
• Xilinx is ISO-TS16949 compliant
• AEC-Q100 qualification
• Production Part Approval Process (PPAP) documentation
• Beyond AEC-Q100 qualification is available upon request
• Designed for low cost
• Multiple efficient integrated blocks
• Optimized selection of I/O standards
• Staggered pads
• High-volume plastic wire-bonded packages
• Low static and dynamic power
• 45 nm process optimized for cost and low power
• Hibernate power-down mode for zero power
• Suspend mode maintains state and configuration with multipin wake-up, control enhancement
• High performance 1.2V core voltage (LX and LXT FPGAs, -2 and -3 speed grades)
• Multi-voltage, multi-standard SelectIO interface banks
• Up to 1,080 Mb