MT41K512M16HA-125:ATR

The Twin Die DDR3L SDRAM is a high-speed, CMOS dynamic random access memory device internally configured as two 8-bank DDR3L SDRAM devices. Although each die is tested individually within the dual-die package, some Twin Die test results may vary from a like die tested within a monolithic die package. The DDR3L SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O balls. A single read or write access consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls. The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3L SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3L SDRAM and edge-aligned to the data strobes. Read and write accesses to the DDR3L SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits (including CSn#, BAn, and An) registered coincident with the READ or WRITE command are used to select the rank, bank, and starting column location for the burst access.

• Uses two 4Gb x16 Micron die in one package
• Two ranks (includes dual CS#, ODT, CKE, and ZQ balls)
• VDD = VDDQ = 1.35V (1.283–1.425V); backward compatible to 1.5V operation
• 1.35V center-terminated push/pull I/O
• JEDEC-standard ballout
• Low-profile package
• TC of 0°C to 95°C
• 0°C to 85°C: 8192 refresh cycles in 64ms
• 85°C to 95°C: 8192 refresh cycles in 32ms