AS8C401801-QC166N

The 401801 is a 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMS. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround.Address and control signals are applied to the SRAM during one clock cycle, and two cycles later the associated data cycle occurs, be it read or write.The 401801 contain data I/O, address and control signal registers. Output enable is the only asynchronous signal and can be used to disable the outputs at any given time.A Clock Enable (CEN) pin allows operation of the 401801 to be suspended as long as necessary. All synchronous inputs are ignored when (CEN) is high and the internal device registers will hold their previous values.There are three chip enable pins (CD , CE2, CE2) that allow the user to deselect the device when desired. If any one of these three are not asserted when ADV/LD is low, no new memory operation can be initiated. However, any pending data transfers (reads or writes) will be completed. The data bus will tri-state two cycles after chip is deselected or a write is initiated.

• 128K x 36, 256K x 18 memory configurations
• Supports high performance system speed - 166 MHz (x18) (3.2 ns Clock-to-Data Access)
• Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access)
• ZBTTM Feature - No dead cycles between write and read cycles
• Internally synchronized output buffer enable eliminates the need to control OE
• Single R/W (READ/WRITE) control pin
• Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications
• 4-word burst capability (interleaved or linear)
• Individual byte write (BM - BW4) control (May tie active)
• Three chip enables for simple depth expansion
• 3.3V power supply (±5%), 3.3V I/O Supply (VDDQ)
• Optional- Boundary Scan JTAG Interface (IEEE 1149.1 compliant)
• Packaged in a JEDEC standard 100-pin plastic thin quad flatpack (TQFP)