AS7C513B-12TCN

AS7C513B-12TCN is a 5V 32K×16 CMOS SRAM. It is a high performance CMOS 524,288-bit static random access memory (SRAM) device organized as 32,768 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20ns with output enable access times (tOE) of 5, 6, 7, 8ns are ideal for high performance applications. The chip enable input active-low CE permits easy memory expansion with multiple-bank memory systems. The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. Active-low LB controls the lower bits, I/O0 – I/O7, and active-low UB controls the higher bits, I/O8 – I/O15.

• Center power and ground pins
• High speed, 10/12/15/20ns address access time, 5, 6, 7, 8ns output enable access time
• Low power consumption, 605mW/max at 10ns (active), 55mW/max CMOS (standby)
• 6 T 0.18 u CMOS technology
• Easy memory expansion with active-low CE, active-low OE inputs
• TTL- and CMOS-compatible, three-state I/O
• 44-pin JEDEC standard packages
• ESD protection is = 2000volts, latch-up current is = 200mA
• 12ns access time, TSOP 2 package
• Commercial temperature range from 0 to 70°C