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AS7C31024B-10TCN

SRAM Chip Async Single 3.3V 1M-Bit 128K x 8 10ns 32-Pin TSOP-I

Manufacturer:Alliance Memory
Product Category: Memory, SRAMs
Avnet Manufacturer Part #: AS7C31024B-10TCN
Secondary Manufacturer Part#: AS7C31024B-10TCN
  • Legend Information Icon RoHS 10 Compliant
  • Legend Information Icon Tariff Charges

The AS7C31024B is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank systems.When CE1 is high or CE2 is low, the device enters standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full standby power is reached (ISB1). For example, the AS7C31024B is guaranteed not to exceed 18 mW under nominal full standby conditions.A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0 through I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode.

  • Industrial and commercial temperatures
  • Organization: 131,072 words x 8 bits
  • High speed
    • 10/12/15/20 ns address access time
    • 5, 6, 7, 8 ns output enable access time
  • Low power consumption: ACTIVE
    • 252 mW / max @ 10 ns
  • Low power consumption: STANDBY
    • 18 mW / max CMOS
  • 6T 0.18u CMOS technology
  • Easy memory expansion with CE1, CE2, OE inputs
  • TTL/LVTTL-compatible, three-state I/O
  • 32-pin JEDEC standard packages
    • 300 mil SOJ
    • 400 mil SOJ
    • 8 × 20mm TSOP 1
    • 8 x 13.4mm sTSOP 1
  • ESD protection = 2000 volts
  • Latch-up current = 200 mA

Technical Attributes

Find Similar Parts

Description Value
17 Bit
1 Mbit
70 mA
10 ns
1 Kb
Surface Mount
32
8 Bit
8 Bit
1
128 kWords
0 to 70 °C
70 °C
0 °C
32TSOP-I
32
8.2 x 18.6 x 1.05 mm
No
Commercial
CMOS SRAM
TSOP-I
3.3 V
Asynchronous
3.3000 V

ECCN / UNSPSC / COO

Description Value
Country of Origin: RECOVERY FEE
ECCN: EAR99
HTSN: 8542320041
Schedule B: 8542320040
In Stock :  0
Additional inventory
Factory Lead Time: 140 Weeks
Price for: Each
Quantity:
Min:156  Mult:156  
USD $:
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$3.7534
5148+
$3.666
10296+
$3.6472
20592+
$3.6284
41184+
$3.6096