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AS7C1025B-15JCN

SRAM Chip Async Single 5V 1M-Bit 128K x 8 15ns 32-Pin SOJ

Manufacturer:Alliance Memory
Product Category: Memory, SRAMs
Avnet Manufacturer Part #: AS7C1025B-15JCN
Secondary Manufacturer Part#: AS7C1025B-15JCN
  • Legend Information Icon RoHS 10 Compliant
  • Legend Information Icon Tariff Charges

The AS7C1025B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as 131,072 x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6/7/8 ns are ideal for highperformance applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory systems. When CE is high, the device enters standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full standby power is reached (ISB1). For example, the AS7C1026B is guaranteed not to exceed 55 mW under nominal full standby conditions. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output drivers stay in high-impedance mode.All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The AS7C1025B is packaged in common industry standard packages.

  • Industrial and commercial temperatures
  • Organization: 131,072 x 8 bits
  • High speed
    • 10/12/15/20 ns address access time
    • 5/6/7/8 ns output enable access time
  • Low power consumption: ACTIVE
    • 605mW / max @ 10 ns
  • Low power consumption: STANDBY
    • 55 mW / max CMOS
  • 6 T 0.18 u CMOS technology
  • Easy memory expansion with CE, OE inputs
  • Center power and ground
  • TTL/LVTTL-compatible, three-state I/O
  • JEDEC-standard packages
    • 32-pin, 300 mil SOJ
    • 32-pin, 400 mil SOJ
  • ESD protection = 2000 volts
  • Latch-up current = 200 mA

Technical Attributes

Find Similar Parts

Description Value
17 Bit
1 Mbit
90 mA
15 ns
1 Kb
Surface Mount
32
8 Bit
8 Bit
1
128 kWords
0 to 70 °C
70 °C
0 °C
32SOJ
32
21.08 x 10.29 x 2.92 mm
No
Commercial
CMOS SRAM
SOJ
5 V
Asynchronous
5.0000 V

ECCN / UNSPSC / COO

Description Value
Country of Origin: RECOVERY FEE
ECCN: EAR99
HTSN: 8542320041
Schedule B: 8542320040
In Stock :  0
Additional inventory
Factory Lead Time: 56 Weeks
Price for: Each
Quantity:
Min:210  Mult:21  
USD $:
210+
$3.8416
5019+
$3.75375
10038+
$0
20076+
$3.71525
40152+
$3.696