AS6C1008-55SIN
SRAM Chip Async Single 3V 1M-Bit 128K x 8 55ns 32-Pin SOP
- RoHS 10 Compliant
- Tariff Charges
The AS6C1008-55SIN is a 1,048,576-bit low power CMOS Static Random Access Memory (SRAM) organized as 131,072 words by 8bits. It is fabricated using very high performance, high reliability CMO S technology. Its standby current is stable within the range of operating temperature. It is well designed for very low power system applications and particularly well suited for battery back-up non-volatile memory application.
- 55ns Access time
- Low power consumption
- 10mA (typical) Operating current
- 1µA (typical) Standby current
- Fully static operation
- Tri-state output
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| 17 Bit | ||
| 1 Mbit | ||
| SOP | ||
| Surface Mount | ||
| 60 mA | ||
| 55 ns | ||
| 128K x 8bit | ||
| 1 Mbit | ||
| Surface Mount | ||
| 32 | ||
| 8 Bit | ||
| 8 Bit | ||
| 1 | ||
| 128 kWords | ||
| -40 to 85 °C | ||
| 85 °C | ||
| -40 °C | ||
| 32SOP | ||
| 32 | ||
| 20.75 x 11.3 x 2.82 mm | ||
| No | ||
| Industrial | ||
| Asynchronous SRAM | ||
| SOP | ||
| 5.5 V | ||
| 2.7 V | ||
| 3 V | ||
| Asynchronous | ||
| 3.0000 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542320041 |
| Schedule B: | 8542320040 |