AS4C64M32MD1-5BIN

The AS4C64M32MD1 is a four bank mobile DDR DRAM organized as 4 banks x 16M x 32. It achieves high speed data transfer rates by employing a chip architecture that pre-fetches multiple bits and then synchronizes the output data to a system clock.All of the controls, address, circuits are synchronized with the positive edge of an externally supplied clock. I/O transactions are possible on both edges of DQS.Operating the four memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device.Additionally, the device supports low power saving features like PASR, Auto-TCSR, DPD as well as options for different drive strength. It’s ideally suitable for mobile application.

• 4 banks x 16M x 32 organization
• Two Die
• stacked 4 banks x 16M x 16
• Data Mask for Write Control (DM)
• Four Banks controlled by BA0 & BA1
• Programmable CAS Latency: 2, 3
• Programmable Wrap Sequence:
  • Sequential or Interleave
• Programmable Burst Length:
  • 2, 4, 8, for Sequential Type
  • 2, 4, 8, for Interleave Type
• Automatic and Controlled Precharge Command
• Power Down Mode
• Auto Refresh and Self Refresh
• Refresh Interval: 8192 cycles/64ms
• Available in 90
• ball BGA
• Double Data Rate (DDR)
• Bidirectional Data Strobe (DQS) for input and output data, active on both edges
• Differential clock inputs CLK and /CLK
• Power Supply 1.7V
• 1.95V
• Drive Strength (DS) Option:Full, 1/2, 1/4, 1/8
• Auto Temperature
• Compensated Self Refresh (Auto TCSR)
• Partial
• Array Self Refresh (PASR) Option: F