AS4C64M16MD1A-5BIN

The AS4C64M16MD1 is a four bank mobile DDR DRAM organized as 4 banks x 16M x 16. It achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock.All of the control, address, circuits is synchronized with the positive edge of an externally sup- plied clock. I/O transactions are possible on both edges of DQS.Operating the four memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device.Additionally, the device supports low power saving featureslike PASR, Auto-TCSR,DPD as well as options for different drive strength. It’s ideally suitable for mobile application.

• 4 banks x 16M x 16 organization
• Data Mask for Write Control (DM)
• Four Banks controlled by BA0 & BA1
• Programmable CAS Latency: 2, 3
• Programmable Wrap Sequence: Sequential orInterleave
• Programmable Burst Length:
  • 2, 4, 8 or 16 for Sequential Type
  • 2, 4, 8 or 16 for Interleave Type
• Automatic and Controlled Precharge Command
• Power Down Mode
• Auto Refresh and Self Refresh
• Refresh Interval: 8192 cycles/64ms
• Double Data Rate (DDR)
• Bidirectional Data Strobe (DQS) for input and output data, active on both edges
• Differential clock inputs CLK and /CLK
• Power Supply 1.7V
• 1.95V
• Drive Strength (DS) Option: Full, 1/2, 1/4, 1/8
• Auto Temperature
• Compensated Self Refresh (Auto TCSR)
• Partial
• Array Self Refresh (PASR) Option: Full, 1/2, 1/4, 1/8, 1/16
• Deep Power Down (DPD) mode
• Operating Temperature Range
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