AS4C64M16D3LC-12BIN

AS4C64M16D3LC-12BIN is a 64M x 16bit DDR3L synchronous DRAM (SDRAM). The 1Gb double-data-rate-3L (DDR3L) DRAMs is a double data rate architecture to achieve high-speed operation. It is internally configured as an eight-bank DRAM. The 1Gb chip is organized as 8Mbit x 16 I/Os x 8 bank devices. It achieves high-speed double-data-rate transfer rates of up to 1600Mb/sec/pin for general applications. The chip is designed to comply with all DDR3L DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with differential DQS pairs in a source-synchronous fashion.

• JEDEC standard compliant, supports JEDEC clock jitter specification
• Fully synchronous operation, fast clock rate: 800MHz, differential clock, CK and CK#
• Bidirectional differential data strobe, DQS and DQS#, 8 internal banks for concurrent operation
• 8n-bit prefetch architecture, pipelined internal architecture, precharge and active power down
• Programmable mode and extended mode registers, additive latency (AL): 0, CL-1, CL-2
• Programmable burst lengths: 4, 8, burst type: sequential/interleave, output driver impedance control
• Auto refresh and self refresh, write levelling
• ZQ calibration, dynamic ODT (Rtt-Nom and Rtt-WR)
• 96-ball FBGA package
• Industrial temperature range from -40°C to 95°C