AS4C64M16D3LB-12BCN

The 1Gb Double-Data-Rate-3 (DDR3L) DRAMs isdouble data rate architecture to achieve high-speedoperation. It is internally configured as an eight bankDRAM.The 1Gb chip is organized as 8Mbit x 16 I/Os x 8bank devices. These synchronous devices achieve highspeed double-data-rate transfer rates of up to 1600Mb/sec/pin for general applications.The chip is designed to comply with all key DDR3LDRAM key features and all of the control and addressinputs are synchronized with a pair of externallysupplied differential clocks. Inputs are latched at thecross point of differential clocks (CK rising and CK#falling). All I/Os are synchronized with differential DQSpair in a source synchronous fashion.These devices operate with a single 1.35V -0.067V/+0.1V power supply and are available in BGApackages.

• JEDEC Standard Compliant
• Power supplies: VDD & VDDQ = +1.35V
• Backward compatible: VDD & VDDQ = 1.5V +/-0.075V
• Operating temperature:
  • Commercial (0 ~ 95°C)
  • Industrial (-40 ~ 95°C)
• Supports JEDEC clock jitter specification
• Fully synchronous operation
• Fast clock rate: 800MHz
• Differential Clock, CK & CK#
• Bidirectional differential data strobe
  • DQS & DQS#
• 8 internal banks for concurrent operation
• 8n-bit prefetch architecture
• Internal pipeline architecture
• Precharge & active power down
• Programmable Mode & Extended Mode registers
• Additive Latency (AL): 0, CL-1, CL-2
• Programmable Burst lengths: 4, 8
• Burst type: Sequential / Interleave
• Output Driver Impedance Control
• 8192 refresh cycles / 64ms
  • Average refresh period 7.8µs @ -40°C ?TC? +85°C 3.9µs @ +85°C