AS4C64M16D2A-25BCN

AS4C64M16D2A-25BCN is a high-speed CMOS double data-rate-two (DDR2), synchronous dynamic random-access memory (SDRAM) containing 1024Mbits in a 16-bit wide data I/Os. It is internally configured as a 8-bank DRAM, 8 banks x 8Mb addresses x 16 I/Os. The device is designed to comply with DDR2 DRAM key features such as posted CAS# with additive latency, write latency = read latency -1, off-chip driver (OCD) impedance adjustment, and on die termination (ODT). read and write accesses to the DDR2 SDRAM are 4 or 8-bit burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Operating the eight memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence.

• JEDEC standard compliant, JEDEC standard 1.8V I/O (SSTL-18-compatible)
• Power supplies: VDD and VDDQ = +1.8V ± 0.1V, 64Mx16 org
• Supports JEDEC clock jitter specification, fully synchronous operation
• Fast clock rate: 400MHz, differential clock, CK and CK#, internal pipeline architecture
• Bidirectional single/differential data strobe, DQS and DQS#, 8192 refresh cycles / 64ms
• 8 internal banks for concurrent operation, 4-bit prefetch architecture
• Precharge and active power down, programmable mode and extended mode registers
• Posted CAS# additive latency (AL): 0, 1, 2, 3, 4, 5,6, WRITE latency = READ latency - 1 tCK
• Burst lengths: 4 or 8, burst type: sequential / interleave, DLL enable/disable
• 84-ball FBGA package, commercial temperature range from 0°C to +85°C