AS4C64M16D1-6TCN

The AS4C64M16D1 is a four bank DDR DRAM organized as 4 banks x 16Mbit x 16. The AS4C64M16D1 achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock.All of the controls, address, circuits are synchronized with the positive edge of an externally supplied clock. I/O transactions are occurring on both edges of DQS.Operating the four memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device.

• High speed data transfer rates with system frequency up to 200MHz
• Data Mask for Write Control
• Four Banks controlled by BA0 & BA1
• Programmable CAS Latency: 2, 2.5, 3
• Programmable Wrap Sequence:
  • Sequential or Interleave
• Programmable Burst
  • Length: 2, 4, 8 for Sequential Type 2, 4, 8 for Interleave Type
• Automatic and Controlled Precharge Command
• Power Down Mode
• Auto Refresh and Self Refresh
• Refresh Interval: 8192 cycles/64 ms
• Available in 66 Pin TSOP II
• SSTL
• 2 Compatible I/Os
• Double Data Rate (DDR)
• Bidirectional Data Strobe (DQS) for input and output data, active on both edges
• On
• Chip DLL aligns DQ and DQs transitions with CK transitions
• Differential clock inputs CK and CK
• VDD = 2.5V ± 0.2V, VDDQ = 2.5V ± 0.2V, VDD = 2.6V ± 0.1V, VDDQ = 2.6V ± 0.1V (DDR400)
• tRAS lockout supported
• Concu