AS4C512M8D4-83BCN

AS4C512M8D4-83BCN is a 512M x 8-bit DDR4 synchronous DRAM (SDRAM). The DDR4 SDRAM is a high-speed dynamic random-access memory internally organized with sixteen banks (4 bank groups each with 4 banks). The DDR4 SDRAM uses an 8n prefetch architecture to achieve highspeed operation. The 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and eight corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read and write operations to the DDR4 SDRAM are burst-oriented, start at a selected location, and continue for a burst length of eight or a ‘chopped’ burst of four in a programmed sequence. Operation begins with the registration of an Activate Command, which is then followed by a Read or Write command.

• JEDEC standard compliant, supports JEDEC clock jitter specification, 1200MHz max clock
• Bidirectional differential data strobe, DQS and DQS#, differential clock, CK and CK#
• 16 internal banks: 4 groups of 4 banks each, separated IO gating structures by bank group
• 8n-bit prefetch architecture, precharge and active power down, auto refresh and self refresh
• Low-power auto self-refresh (LPASR), self refresh abort, fine granularity refresh
• Dynamic ODT (RTT-PARK and RTT-Nom and RTT-WR), write levelling, DQ training via MPR
• Internal VREFDQ training, read preamble training, control gear down mode
• ZQ calibration, command/address latency (CAL), maximum power saving mode (MPSM)
• Asynchronous reset, DLL enable/disable, CAS latency (CL), CAS write latency (CWL)
• 78-ball FBGA package, commercial (extended) temperature range from 0°C to 95°C