AS4C512M8D3LC-12BCN

AS4C512M8D3LC-12BCN is a 512M x 8-bit DDR3L synchronous DRAM (SDRAM). The 4Gb double-data-rate-3 (DDR3L) DRAMs is a double data rate architecture to achieve high-speed operation. It is internally configured as an eight-bank DRAM. The 4Gb chip is organized as 64Mbit x 8 I/Os x 8 bank devices. This synchronous device achieves high-speed double-data-rate transfer rates of up to 1600Mb/sec/pin for general applications. The chip is designed to comply with all key DDR3L DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with differential DQS pairs in a source-synchronous fashion.

• JEDEC standard compliant, supports JEDEC clock jitter specification
• Power supplies: VDD and VDDQ=1.35V (1.283 to 1.45V), backward compatible to VDD and VDDQ=1.5±0.075V
• Fully synchronous operation, fast clock rate: 800MHz, differential clock, CK and CK#
• Bidirectional differential data strobe, DQS & DQS#, 8 internal banks for concurrent operation
• 8n-bit prefetch architecture, pipelined internal architecture, precharge and active power down
• Programmable mode and extended mode registers, additive latency (AL): 0, CL-1, CL-2
• Programmable burst lengths: 4, 8, burst type: sequential/interleave
• Output driver impedance control, write levelling, ZQ calibration
• Dynamic ODT (Rtt-Nom and Rtt-WR), auto refresh and self refresh
• 78-ball FBGA package, commercial temperature range from 0°C to 95°C