AS4C4M32SA-6TIN

AS4C4M32SA-6TIN is a high-speed, 128Mb CMOS synchronous DRAM containing 134,217,728Mbits. It is internally configured as a quad 1M x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 1M x 32-bit banks is organized as 4096 rows by 256 columns by 32 bits. Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a read or write command. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. It is well suited for applications requiring high memory bandwidth.

• Fully synchronous operation, internal pipelined architecture
• Four internal banks (1M x 32-bit x 4bank)
• Programmable mode, CAS latency: 2 or 3, burst length: 1, 2, 4, 8, or full page
• Burst type: sequential and interleaved, burst-read-single-write
• Burst stop function, individual byte controlled by DQM0-3
• Auto refresh and self-refresh, 4096 refresh cycles/64ms
• Single 3.3V ±0.3V power supply, LVTTL interface
• 166MHz maximum clock
• 86-pin TSOP II package
• Industrial temperature range from -40°C to +85°C