AS4C32M16D2A-25BCN

AS4C32M16D2A-25BCN is a 32M x 16bit DDR2 synchronous DRAM (SDRAM). It is a high-speed CMOS double-data-rate-two (DDR2), synchronous dynamic random-access memory (SDRAM) containing 512Mbits in a 16-bit wide data I/Os. It is internally configured as a quad bank DRAM, 4 banks x 8Mb addresses x 16 I/Os. The device is designed to comply with DDR2 DRAM key features such as posted CAS# with additive latency, write latency = read latency -1, off-chip driver (OCD) impedance adjustment, and on die termination(ODT). All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS#) in a source synchronous fashion. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence.