AS4C32M16D2-25BCNTR

The AS4C32M16D2 DDR2 SDRAM is a high-speed CMOSDouble-Data-Rate-Two (DDR2), synchronous dynamicrandom-access memory (SDRAM) containing 512 Mbits ina 16-bit wide data I/Os. It is internally configured as a quadbank DRAM, 4 banks x 8Mb addresses x 16 I/OsThe device is designed to comply with DDR2 DRAM keyfeatures such as posted CAS# with additive latency, Writelatency = Read latency -1, Off-Chip Driver (OCD) impedanceadjustment, and On Die Termination(ODT).All of the control and address inputs are synchronizedwith a pair of externally supplied differential clocks. Inputsare latched at the cross point of differential clocks (CKrising and CK# falling)All I/Os are synchronized with a pair of bidirectionalstrobes (DQS and DQS#) in a source synchronous fashion.The address bus is used to convey row, column, and bankaddress information in RAS #, CAS# multiplexing style. Accesses begin with theregistration of a Bank Activate command, and then it isfollowed by a Read or Write command. Read and writeaccesses to the DDR2 SDRAM are 4 or 8-bit burst oriented;accesses start at a selected location and continue for aprogrammed number of locations in a programmedsequence. Operating the four memory banks in aninterleaved fashion allows random access operation tooccur at a higher rate than is possible with standardDRAMs. An auto precharge function may be enabled toprovide a self-timed row precharge that is initiated at theend of the burst sequence. A sequential and gapless datarate is possible depending on burst length, CAS latency,and speed grade of the device.

• JEDEC Standard Compliant
• JEDEC standard 1.8V I/O (SSTL_18
  • compatible)
• Power supplies: VDD & VDDQ = +1.8V ? 0.1V
• Supports JEDEC clock jitter specification
• Fully synchronous operation
• Fast clock rate: 400 MHz
• Differential Clock, CK & CK#
• Bidirectional single/differential data strobe
  • DQS & DQS#
• 4 internal banks for concurrent operation
• 4
  • bit prefetch architecture
• Internal pipeline architecture
• Precharge & active power down
• Programmable Mode & Extended Mode registers
• Posted CAS# additive latency (AL): 0, 1, 2, 3, 4, 5, 6
• WRITE latency = READ latency
  • 1 tCK
• Burst lengths: 4 or 8
• Burst type: Sequential / Interleave
• DLL enable/disable
• Off
  • Chip Driver (OCD)
  • Impedance Adjustment
  • Adjustable data
  • output drive strength
• On
  • d