AS4C2M32SA-6TCN

AS4C2M32SA-6TCN 64Mb SDRAM is a high-speed CMOS synchronous DRAM containing 67,108,864bits. It is internally configured as a quad 512K x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 32bit banks is organized as 2048 rows by 256 columns by 32bits. Read and write accesses to SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a bank activate command which is then followed by a read or write command. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. By having a programmable mode register, the system can choose most suitable modes to maximize its performance. It is well suited for applications requiring high memory bandwidth.

• Fully synchronous operation, internal pipelined architecture
• Four internal banks (512K x 32bit x 4bank)
• Programmable mode, CAS latency: 2 or 3, burst length: 1, 2, 4, 8, or full page
• Burst stop function, individual byte controlled by DQM0-3
• Auto refresh and self refresh, 4096 refresh cycles/64ms
• Single +3.3V ±0.3V power supply
• LVTTL interface
• 2M x 32 org, 166MHz maximum clock
• 86-pin TSOP II package
• Commercial temperature range from 0°C to +70°C