AS4C2M32S-7BCN

AS4C2M32S-7BCN is a 2M x 32bit synchronous DRAM (SDRAM). The 64Mb SDRAM is a high-speed CMOS synchronous DRAM containing 64 Mbits. It is internally configured as a quad 512K x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 32bit banks is organized as 2048 rows by 256 columns by 32 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. It is well suited for applications requiring high memory bandwidth.

• Fully synchronous operation, internal pipelined architecture
• Four internal banks (512K x 32bit x 4bank)
• Programmable mode, CAS latency: 2 or 3, burst length: 1, 2, 4, 8, or full page
• Burst type: sequential or interleaved, burst-read-single-write, burst stop function
• Individual byte controlled by DQM0-3, auto refresh and self refresh
• 4096 refresh cycles/64ms, single +3.3V ±0.3V power supply
• LVTTL interface
• 143MHz frequency
• 90-ball TFBGA package
• Commercial temperature range from 0 to 70°C